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Quasi Delay Insensitive
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#	Item
11	1 Slack Matching Quasi Delay-Insensitive Circuits Piyush Prakash, Alain J. Martin Department of Computer Science California Institute of Technology Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2006-12-08 14:20:38 Graph theory Convex optimization Linear programming Operations research Matching Retiming Graph Mathematics Theoretical computer science Applied mathematics
12	Microsoft Word - Formalizing and Improving DPA resistance DATE2005.doc Add to Reading List Source URL: www.ssi.gouv.fr Language: English - Date: 2012-11-06 05:29:24 Electrical circuits Digital electronics Synchronization Asynchronous circuit Clock signal Quasi Delay Insensitive Capacitor Side channel attack Asynchrony Electronic engineering Electronics Electrical engineering
13	Rapid Prototyping of Self-timed Circuits S.W. Moore and P. Robinson University of Cambridge, Computer Laboratory, Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2000-12-21 11:17:11 Electrical circuits Logic gates Electronic design automation Digital electronics Flip-flop Quasi Delay Insensitive Field-programmable gate array Arbiter Verilog Electronic engineering Electronics Electrical engineering
14	Overview Asynchronous Circuit Design Add to Reading List Source URL: www.async.ece.utah.edu Language: English - Date: 2009-04-20 19:15:50 Electromagnetism Asynchronous circuit Asynchrony Delay insensitive circuit Digital electronics Arbiter Central processing unit Clock signal Quasi Delay Insensitive Electronic engineering Electrical circuits Electrical engineering
15	Quasi-delay-insensitive circuits are Turing-completey RVM33 -1 Add to Reading List Source URL: vlsi.cornell.edu Language: English - Date: 2008-06-20 13:43:02 Theory of computation Computability theory Quasi Delay Insensitive Turing machine Delay insensitive circuit Computability Circuit Theoretical computer science Models of computation Computer science
16	Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding Add to Reading List Source URL: www.date-conference.com Language: English - Date: 2006-02-13 13:52:04 Digital electronics Electrical circuits Electronic design Computer memory Asynchronous circuit Clock signal Delay insensitive circuit Flip-flop Quasi Delay Insensitive Electronic engineering Electrical engineering Electronics
17	PDF Document Add to Reading List Source URL: sld.cs.columbia.edu Language: English - Date: 2012-02-03 22:48:50 Central processing unit Latency Computer memory Digital electronics Delay insensitive circuit Pipeline Transmission Control Protocol Quasi Delay Insensitive Flip-flop Electronic engineering Computer architecture Engineering

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